Job Description

Job Summary:

Job Title: FPGA Engineer

Job ID: 536707

Client: Eaton

Location: Raleigh, NC

Experience Level: 5–7 Years

Job Description & Skill Requirement:

1. Verilog & VHDL RTL Design
2. FPGA Design & Debug
3. CDC & Interface Protocols Understanding

• Requirement of 5-7 Years FPGA Engineers having below skills
• Strong Verilog HDL and RTL design expertise.
• Good knowledge of CDC, reset design, pipelining, FIFO/memory, and synchronization.
• Experience with FPGA tools like Vivado, Quartus, Libero, Questa/ModelSim.
• Strong understanding of STA, timing constraints, timing closure, and clock architecture.
• Hands-on experience in FPGA hardware bring-up and debugging

Relevant Industries & Company Locations to Focus:

• Industries: Semiconductor, FPGA Design, Embedded Systems, Electronics, Hardware Engineering.
• Target Companies: FPGA development, semiconductor, and electronics hardware companies.
• Locations: Raleigh, NC, and candidates open to working onsite in Raleigh.

Priority 1

• 5–7 years of FPGA engineering experience.
• Strong Verilog HDL and VHDL RTL design.
• FPGA design, debugging, and hardware bring-up.
• CDC (Clock Domain Crossing) and synchronization.
• STA, timing constraints, and timing closure.

Priority 2

• Experience with Vivado, Quartus, or Libero.
• Knowledge of Questa/ModelSim simulation tools.
• Experience with reset design, pipelining, FIFO, and memory.
• Understanding of clock architecture and interface protocols.

Nice to Have:

• Hands-on FPGA board-level debugging.
• Experience resolving timing and synchronization issues.
• Knowledge of multiple FPGA design tools.

What to Look for on Resume:

• Verilog/VHDL RTL coding experience.
• FPGA implementation and debugging projects.
• CDC, STA, and timing closure experience.
• FPGA tools: Vivado, Quartus, or Libero.
• Hardware bring-up and real-board debugging experience.

Do Not Consider:

• Candidates without FPGA design experience.
• Candidates with only software development experience.
• Candidates without Verilog/VHDL RTL design skills.
• Candidates lacking hardware debugging experience.
• Candidates with significantly less or more experience than the required 5–7 years.

Education & Experience:

• Experience: 5–7 years in FPGA engineering.
• Education: Relevant degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.

Benefits: Eligible employees may have access to benefits offered by Intellectt Inc. in accordance with the applicable benefit plans and eligibility requirements.

Equal Employment Opportunity:

Intellectt Inc. is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, disability, genetic information, veteran status, or any other characteristic protected by applicable federal, state, or local law.

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