Job Description

Job Description

1. Verilog & VHDL RTL Design
2. FPGA Design & Debug
3. CDC & Interface Protocols Understanding

• Requirement of 5-7 Years FPGA Engineers having below skills
• Strong Verilog HDL and RTL design expertise.
• Good knowledge of CDC, reset design, pipelining, FIFO/memory, and synchronization.
• Experience with FPGA tools like Vivado, Quartus, Libero, Questa/ModelSim.
• Strong understanding of STA, timing constraints, timing closure, and clock architecture.
• Hands-on experience in FPGA hardware bring-up and debugging

Benefits:

Eligible employees may enroll in and receive benefits offered by Intellectt Inc., subject to applicable plan terms, eligibility criteria, and contribution requirements.

Equal Employment Opportunity:

Intellectt Inc. is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, disability, genetic information, veteran status, or any other characteristic protected by applicable federal, state, or local law.

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